As transmission/reception select switches in portable electronic devices such as mobile phones, compound semiconductor elements have been used in the past. However, the improvement in the high-frequency characteristics of silicon MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) that has been achieved by forming silicon MOSFETs on SOI (Silicon on Insulator) substrates or SOS (Silicon on Sapphire) substrates is remarkable in recent years. As a result, opportunities for silicon MOSFETs to be applied as high-frequency switches of portable electronic devices are increasing.
A transmission loss, a harmonic distortion, and an inter-modulation distortion (IMD) are some examples of the important characteristics that indicate the performance of a high-frequency switch. These characteristics can be improved by reducing the CR product that is the product of the parasitic capacitance C and the on-resistance R of the MOSFET.
Therefore, it has been attempted to reduce the parasitic capacitance C and the on-resistance R by reducing the element size of a MOSFET and thereby reducing the channel length. As a method for reducing a parasitic capacitance C, reduction in the capacitance of source/drain diffusion layers and the miniaturization of a gate length achieved by adopting a thin-film SOI substrate have been known. A thin-film SOI substrate used for such purposes is manufactured, for example, by a smart-cut method.
A typical semiconductor device in which MOSFETs are formed on an SOI substrate (Patent literature 1) is explained. FIG. 5 is a cross section showing a structure of a typical semiconductor device 300 in which MOSFETs are formed on an SOI substrate. In the semiconductor device 300, the SOI substrate includes a p-type silicon substrate 314. The silicon substrate 314 includes a first region 310 and a second region 312. A high voltage transistor 313 is formed in the first region 310. Other examples of the semiconductor element that can be formed in the first region 310 include a vertical bipolar transistor. A MOS field-effect transistor 315 having an SOI structure is formed in the second region 312. Examples of the circuit that can be formed in the second region 312 include a circuit for which a high-speed operation or low power consumption is necessary (for example, a circuit used in a portable information device or the like).
Next, details of the first region 310 are explained. The high voltage transistor 313 includes a gate electrode 340, source/drain 334a and 336a, and source/drain offsets 334b and 336b. A p-type well 316 is formed in the silicon substrate 314 in the first region 310. A gate oxide film 338 is formed on the well 316. The thickness of the gate oxide film 338 is, for example, 40 to 100 nm. Offset LOCOS oxide films 322 and 324 are formed above the well 316 so as to sandwich the gate oxide film 338 therebetween. The gate electrode 340 is formed on the gate oxide film 338. One end of the gate electrode 340 is located on the offset LOCOS oxide film 322. The other end of the gate electrode 340 is located on the offset LOCOS oxide film 324.
An n-type source/drain offset 334b is formed in the well 316 beneath the offset LOCOS oxide film 322. An n-type source/drain 334a is formed in the well 316. The n-type source/drain 334a is located beside the source/drain offset 334b. An n-type source/drain offset 336b is formed in the well 316 beneath the offset LOCOS oxide film 324. An n-type source/drain 336a is formed in the well 316. The n-type source/drain 336a is located beside the source/drain offset 336b. 
An element separation LOCOS oxide film 326 is formed at one end of the well 316, and an element separation LOCOS oxide film 320 is formed at the other end of the well 316. A p-type channel stopper region 330 is formed in the well 316 beneath the element separation LOCOS oxide film 326. A p-type channel stopper region 332 is formed in the well 316 beneath the element separation LOCOS oxide film 320. An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 340. A through hole 342 for exposing the source/drain 334a is formed in the inter-layer insulating film 350. An aluminum line 346 is formed on the inter-layer insulating film 350. The aluminum line 346 is also formed inside the through hole 342 and electrically connected to the source/drain 334a. A through hole 344 for exposing the source/drain 336a is formed in the inter-layer insulating film 350. An aluminum line 348 is formed on the inter-layer insulating film 350. The aluminum line 348 is also formed inside the through hole 344 and electrically connected to the source/drain 336a. 
Next, details of the second region 312 are explained. The MOS field-effect transistor 315 includes a gate electrode 360 and source/drain 354 and 356. A buried oxide film 318 is formed on the silicon substrate 314 in the second region 312. A silicon single-crystal layer is formed on the buried oxide film 318. A p-type body region 352 and n-type source/drain 354 and 356 are formed in this silicon single-crystal layer. Element separation LOCOS oxide films 326 and 328 are formed on the buried oxide film 318. The MOS field-effect transistor 315 is insulated and separated from other elements by the element separation LOCOS oxide films 326 and 328.
A gate oxide film 358 is formed on the body region 352. The thickness of the gate oxide film 358 is, for example, 3 to 10 nm. An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 360. A through hole 362 for exposing the source/drain 354 is formed in the inter-layer insulating film 350. An aluminum line 366 is formed on the inter-layer insulating film 350. The aluminum line 366 is also formed inside the through hole 362 and electrically connected to the source/drain 354. A through hole 364 for exposing the source/drain 356 is formed in the inter-layer insulating film 350. An aluminum line 368 is formed on the inter-layer insulating film 350. The aluminum line 368 is also formed inside the through hole 364 and electrically connected to the source/drain 356.
That is, it is possible in the semiconductor device 300 to form both a high voltage MOSFET requiring a deep diffusion layer and a MOSFET having an SOI structure in the same substrate.
Further, a drive circuit capable of controlling a slew rate with ease while preventing the increase in the circuit size has been proposed (Patent literature 2). Further, semiconductor devices of similar types have been disclosed (Patent literatures 3 and 4).